Hear The Brilliant Minds Accelerating Adoption Of Multi-Die Systems

As Moore’s Law has slowed, engineers have faced numerous challenges in their attempts to address the ever-evolving needs of the demanding semiconductor and electronics industries. The historic power, area, and performance benefits that traditionally came by shrinking chips on more advanced fab process nodes have slowed considerably, while complexity has skyrocketed and costs have commensurately increased. That reality was simply unsustainable in the long term and forced engineers to devise creative solutions. It turns out that virtually all of the major players in the space turned to multi-die systems, which have supplanted large monolithic chips for many applications.

For the uninitiated, multi-die systems are essentially chips that feature multiple silicon dies, often dubbed chiplets, integrated into a single package. The methods used to link those dies or chiplets, however, varies greatly depending on the needs of the manufacturer and ultimate goals for the end product. All of the associated variables with multi-die systems has introduced an enormous amount of complexity that monolithic chip designers of the past didn’t have to contend with.

Synopsys Brings Industry Leaders Together

Industry leader in silicon design and verification, Synopsys, recently hosted a panel to discuss the acceleration of adopting multi-die systems. The panel included experts from Ansys, Bosch, Intel, Samsung, and Synopsys itself. Murat Becer (Ansys), Michael Schaffert (Bosch), Lalitha Immaneni (Intel), Cheolmin Park (Samsung), and Shekhar Kapoor (Synopsys) discussed the increasing adoption of multi-die systems, and detailed a myriad of the challenges associated with multi-die systems and how to overcome them. The discussion also included many insights into potential future innovations and thoughts on how to use them to bring better products to market.

I had the pleasure of moderating the panel and asked questions regarding the state of multi-die system adoption, the techniques used to mitigate potential adoption roadblocks, and how adoption ultimately affects the ecosystem as a whole. To put it simply, the discussion was eye-opening. The participants went into great detail about the challenges related to everything from die-to-die connectivity and test and repair, to software development and power and thermal management. The motivations for or against adopting multi-die systems were discussed at length as well, in addition to the market segments that are poised to lead the charge and benefit from these new technologies.

Multi-Die Systems Are Here To Stay

Needless to say, with compute demands rising and the ever-increasing pervasiveness of advanced technology in our daily lives, multi-die systems will remain at the forefront of chip design for the foreseeable future. The ability to leverage dies from different chip fabrication process technologies, to optimally enable products with specific features and functionality, while also hitting precise performance and power targets, empowers designers with new ways to bring products to market, with more flexibility than ever before. From AI to automotive applications, to mobile devices and data center servers, multi-die systems are the foundation for many bleeding edge products that simply couldn’t be designed using the monolithic chips of the past. And some of the experts that participated in the panel were an integral part in building them.

Whether you have just a passing interest in chips and semiconductors, or are a jaded industry veteran who thinks they’ve heard it all, I recommend watching a recording of this very interesting panel discussion, which is hosted right here. There are a multitude of interesting topics discussed, by experts with differing technology backgrounds and points of view. I have participated in many discussions in over two decades covering chips and technology, and this panel was easily one of my favorites.

Source: www.forbes.com

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